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NTE7495 IC TTL 4−Bit Parallel−Access Shift Register

Model:

NTE7495

 | Catalog #: 55051393
Price:
$3.14
$3.14
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  • Absolute Maximum Ratings:
    Unless otherwise specified, all voltages are referenced to GND
  • Supply voltage, VCC: 7V
  • DC input voltage, VIN: 5.5V
  • Interemitter voltage (voltage between 2 emitters of a multiple−emitter transistor)*: 5.5V
  • Operating temperature range, TA: 0°C to +70°C
  • Storage temperature range, Tstg: −65°C to +150°C

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  • Absolute Maximum Ratings:
    Unless otherwise specified, all voltages are referenced to GND
  • Supply voltage, VCC: 7V
  • DC input voltage, VIN: 5.5V
  • Interemitter voltage (voltage between 2 emitters of a multiple−emitter transistor)*: 5.5V
  • Power dissipation: 130mW
  • Operating temperature range, TA: 0°C to +70°C
  • Storage temperature range, Tstg: −65°C to +150°C

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  • Applications:
  • Digital computer systems
  • Data−handling systems
  • Control systems
  • Absolute Maximum Ratings: (TA= 0° to +70°C unless otherwise specified)
  • Supply voltage VCC (Note 1): 7V
  • Input voltage: 5.5V
  • Power dissipation: 175mW
  • Operating free−air temperature range: 0°C to +70°C
  • Storage temperature range: -65°C to +150°C
  • Voltage values are with respect to network ground terminal

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Product Summary

The NTE7495 is 4-bit register in a 14-lead DIP-type package that features parallel and serial inputs, parallel outputs, mode control and two clock inputs. This device has three output modes of operation: parallel (broadside), load shift right (the direction QA toward QD), shift left (the direction QD toward QA) parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock 2 input. During loading, the entry of serial data is inhibited. Shift right is accomplished on the high-to-low transition of clock 1 when the mode control is low; shift left is accomplished on the high-to-low transition of clock 2 when the mode control is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop (QD to input C, etc.) and serial data is entered at input D. The clock input may be applied commonly to clock 1 and clock 2 if both modes can be clocked from the same source. Changes at the mode control input should normally be made while both clock inputs are low; however, conditions described in the last three lines of the function table will also ensure that register contents are protected.

Data Sheet

  • Absolute Maximum Ratings: (Note 1)
  • Supply voltage VCC: 7V
  • Input voltage VIN: 5.5V
  • Interemitter voltage (Note 2): 5.5V
  • Power dissipation: 195mW
  • Operating temperature range, TA: 0°C to +70°C
  • Storage temperature range, Tstg: −65°C to +150°C
Pricing and availability: Please note that all prices are subject to change without prior notice. Prices advertised on this site are for online orders only. Prices on some items may differ from those advertised in RadioShack stores. All merchandise may not be available at all stores, and all stores may not participate in all sales promotions. We recommend you contact the store to confirm product availability and price.

Disclaimer: Note 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. Note 2. This is the voltage between two emitters of a multiple−emitter input transistor. This rating applies between the clock 2 and the mode control input.

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