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The NTE74199 is an 8−bit shift register in a 24−lead DIP-type package compatible with most other TTL and MSI logic families. All inputs are buffered to lower the drive requirements to one normalized series 74 load and input clamping diodes minimize switching transients to simplify system design. Maximum input clock frequency is typically 35MHz and power dissipation is typically 360mW. The NTE74199 register features parallel inputs, parallel outputs, J−K serial inputs, shift/load control input, a direct overriding clear line and gated clock inputs and has three modes of operation:
Inhibit clock (do nothing) Shift (in the direction QA toward QH) Parallel (broadside) load
Parallel loading is accomplished by applying the eight bits of data and taking the shift/load control input low when the clock input is not inhibited. The data is loaded into the associated flip−flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished synchronously when shift/load is high and the clock input is not inhibited. Serial data for this mode is entered at the J−K inputs. See the function table for levels required to enter serial data into the first flip−flop. Both of the clock inputs are identical in function and may be used interchangeably to serve as clock or clock−inhibit inputs. Holding either high inhibits clocking, but when one is held low, a clock input applied to the other input is passed to the eight flip−flops of the register. The clock−inhibit should be changed to the high level only while the clock input is high. This shift register contains the equivalent of 79 TTL gates. Average power dissipation per gate is typically 4.55mW.
Voltage values are with respect to network ground terminal
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