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The NTE74LS74A contains two independent D−type positive−edge−triggered flip−flops in a 14−lead DIP-type package characterized for operating from 0° to +70° C. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive−going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.
Voltage values are with respect to network GND terminal
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