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The NTE7470 is a monolithic, positive-edge-triggered J-K flip-flop in a 14-lead DIP-type package that features gated inputs, direct clear and preset inputs and complementary Q and Q outputs. Input information is transferred to the outputs on the positive edge of the clock pulse. Direct-coupled clock triggering occurs at a specific voltage level of the clock pulse and after the clock input threshold voltage has been passed, the gated inputs are locked out. This flip-flop is ideally suited for medium-to-high-speed applications and can result in a significant saving in system power dissipation and package count where input gating is required.
Voltage values are with respect to network GND terminal
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