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The NTE74278 is a 4−bit cascadable priority register in a 14−lead plastic DIP-type package consisting of four data latches, full priority output gating and a cascading gate. The highest−order data applied at a D latch input is transferred to the appropriate Y output while the strobe input is high and when the strobe goes low all data is latched. The cascading input P0 is fully overriding and on the highest−order package this input must be held at a low logic level. The P1 output is intended for connection to the P0 input of the next lower−order package and will provide a "busy" (high−level) signal to inhibit all subsequent lower−order packages. After the overriding P0 input, the order of priority is D1, D2, D3 and D4 respectively within the package.
Latched data inputs serve as buffer register and can also:
Synchronize data acquisition
Debounce mechanical switch input
Cascading input P0 and output P1 provide "Busy" signal, inhibiting all lower−order bits
Absolute Maximum Ratings: Unless otherwise specified, all voltages are referenced to GND
Supply voltage, VCC: 7V
DC input voltage, VIN: 5.5V
Interemitter voltage (voltage between 2 emitters of a multiple−emitter transistor)*: 5.5V
Operating temperature range, TA: 0°C to +70°C
Storage temperature range, Tstg: −65°C to +150°C
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*For this circuit, this rating applies between the clear and count/load inputs.