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The NTE74105 is a gated J−K master−slave flip−flop in a 14−lead plastic DIP-type package that features a buffered clock input, direct preset and clear, gated J and K inputs and a common JK input.
The clock buffer offers typical TTL high-noise immunity, low clock−line loading, and, in most cases, eliminates the need for stringent control of system−clock rise and fall times. When activated, the direct preset and clear inputs control the state of both the master and slave flip−flops independent of the clock and synchronous−input−states. Gated inputs may be used to perform a wide variety of control functions without the need for external gates, and the common JK input simplifies hardware design for applications utilizing a single gate−control source. Due to the internal clock buffer, the JK input gates accept data when the clock line is low, and transfer of data from the master to the slave occurs during the clock−line transition from the low state to the high state. When the clock line is high, the data inputs are inhibited. The NTE74105 offers an inverting data input to each of the J and K input gates for additional control flexibility. As the input setup and hold times are not lengthened, this circuit permits operation at higher toggle rates.
Absolute Maximum Ratings*:
Supply voltage, VCC: 8V
Input voltage, VIN: 5.5V
Voltage applied to any output**: 5.5V
Operating temperature range, TA: 0°C to +70°C
Storage temperature range, Tstg: −65°C to +150°C
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* Voltage values are with respect to network ground terminal.
** This rating applied at the Q output with preset held low and at the Q output with clear held low.