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The NTE74LS395A is a 4-bit cascadable shift register in a 16-lead plastic DIP-type package that features parallel inputs, parallel outputs and clock (CLK), serial (SER), load shift (LD/SH), output control (OC) an direct overriding clear (CLR) inputs. Shifting is accomplished when the load/shift control is low. Parallel loading is accomplished by applying the four bits of data and taking the load/shift control input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock input. During parallel loading, the entry of serial data is inhibited. When the output control is low, the normal logic levels of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high-logic level at the output control input. The outputs then present high-impedance and neither load nor drive the bus line; however, sequential operation of the registers is not affected. During the high-impedance mode, the output at QD is still available for cascading.
Unless otherwise specified, all voltages are referenced to GND
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