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NTE74LS395A IC TTL 4−Bit Cascadable Shift Register

Model:

NTE74LS395A

 | Catalog #: 55051142
Price:
$2.30
$2.30
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  • Features:
  • Dual version of the popular NTE74LS90
  • Individual clocks for A and B flip−flops provide dual ÷2 and ÷5 counters
  • Direct clear for each 4−bit counter
  • Dual 4−bit versions can improve system densities by reducing counter package count by 50%
  • Typical maximum count frequency: 35MHz
  • Buffered outputs reduce possibility of collector commutation
  • Absolute Maximum Ratings:
  • Supply voltage VCC: 7V
  • Clear input voltage: 7V
  • Any A or B clock input voltage: 5.5V
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: -65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND

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  • Features:
  • Dual version of the popular NTE74LS93
  • Dual 4−bit binary counter with individual clocks
  • Direct clear for each 4−bit counter
  • Dual 4-bit versions can improve system densities by reducing counter package count by 50%
  • Typical maximum count frequency: 35MHz
  • Buffered outputs reduce possibility of collector commutation
  • Absolute Maximum Ratings:
  • Supply voltage VCC: 7V
  • Input voltage: 7V
  • Any A or B clock input voltage: 5.5V
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: -65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND

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  • Features:
  • Parallel access
  • Propagation delay time: 20ns (Typ)
  • Power dissipation: 120mW (Typ)
  • Applications:
  • N−bit storage files
  • Hex/BCD serial−to−parallel converter
  • Absolute Maximum Ratings:
  • Supply voltage VCC: 7V
  • Input voltage: 7V
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: -65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND

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Availability:

ONLINE In stock
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Product Summary

The NTE74LS395A is a 4-bit cascadable shift register in a 16-lead plastic DIP-type package that features parallel inputs, parallel outputs and clock (CLK), serial (SER), load shift (LD/SH), output control (OC) an direct overriding clear (CLR) inputs. Shifting is accomplished when the load/shift control is low. Parallel loading is accomplished by applying the four bits of data and taking the load/shift control input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock input. During parallel loading, the entry of serial data is inhibited. When the output control is low, the normal logic levels of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high-logic level at the output control input. The outputs then present high-impedance and neither load nor drive the bus line; however, sequential operation of the registers is not affected. During the high-impedance mode, the output at QD is still available for cascading.

Data Sheet

  • Features:
  • Three−state, 4−bit, cascadable, parallel−in, parallel−out register
  • Low-power dissipation (enabled): 75mW (Typ)
  • Applications:
  • N−bit serial−to−parallel converter
  • N−bit parallel−to−serial converter
  • N-bit storage register
  • Absolute Maximum Ratings:
  • Supply voltage VCC: 7V
  • Input voltage: 7V
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: -65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND
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