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The NTE74160 thru NTE74163 are synchronous, presettable counters in a 16−lead DIP-type package that feature an internal carry look−ahead for application in high−speed counting designs. The NTE74160 and NTE74162 are decade counters and the NTE74161 and NTE74164 are 4−bit binary counters. Synchronous operation is provided by having all flip−flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. However, counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip−flops on the rising edge of the clock input waveform.
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low−to−high transitions at the load input of the NTE74160 thru NTE74163 should be avoided when the clock is low if the enable inputs are high at or before the transition.
The clear function for the NTE74160 and NTE74161 is asynchronous and a low level at the clear input sets all four of the flip−flop outputs low regardless of the levels of clock, load or enable inputs. The clear function of the NTE74162 and NTE74163 is synchronous and a low level at the clear input sets all four flip−flop out-puts low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low−to−high transitions at the clear input of the NTE74162 and NTE74163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition.
The carry look−ahead circuitry provides for cascading counters for n−bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count enable inputs and a ripple carry output. Both count enable inputs (P and T) must be high to count and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high−level output pulse with a duration approximately equal to the high−level portion of the Q A output. This high−level overflow ripple carry pulse can be used to enable successively cascaded stages. High−to−low−level transitions at the enable P or T inputs should occur only when the clock input is high.
Available in 4 types: decade with direct clear NTE74160, binary with direct clear NTE74161, decade with synchronous clear NTE74162, binary with synchronous clear NTE74163
Internal look−ahead for fast counting
Carry output for n−bit cascading
Load control line
Absolute maximum ratings:
Supply voltage VCC: 7V
DC Input voltage VIN: 5.5V
Interemitter voltage (Note 2): 5.5V
Power dissipation PD: 305mW
Operating temperature range TA: 0°C to +70°C
Storage temperature range Tstg: −65°C to +150°C
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Note 1: unless otherwise specified, all voltages are referenced to GND. Note 2: this is the voltage between two emitters of a multiple−emitter transistor. For these circuits, this rating applies between the count enable inputs P and T.