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NTE74173 IC TTL 4-Bit D Register

Model:

NTE74173

 | Catalog #: 55051328
Price:
$2.21
$2.21
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  • Absolute Maximum Ratings:
    Unless otherwise specified, all voltages are referenced to GND
  • Supply voltage, VCC: 7V
  • DC input voltage, VIN: 5.5V
  • Output voltage (maximum applied to any output in the off state), VO: 15V
  • Operating temperature range, TA: 0°C to +70°C
  • Storage temperature range, Tstg: −65°C to +150°C

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  • DC Input voltage VIN: 5.5V
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  • Power dissipation PD: 210mW
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: −65°C to +150°C

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  • Absolute maximum ratings:
  • Supply voltage VCC: 7V
  • DC Input voltage VIN: 5.5V
  • Power dissipation PD: 21mW
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: −65°C to +150°C
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  • Absolute maximum ratings:
  • Supply voltage VCC: 7V
  • DC Input voltage VIN: 5.5V
  • Interemitter voltage (Note 2): 5.5V
  • Power dissipation PD: 305mW
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: −65°C to +150°C

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  • Absolute maximum ratings:
  • Supply voltage VCC: 7V
  • DC Input voltage VIN: 5.5V
  • Interemitter voltage (Note 2): 5.5V
  • Power dissipation PD: 305mW
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: −65°C to +150°C

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Product Summary

The NTE74173 is a 4−bit register in a 16−lead plastic DIP-type package that includes D−type flip−flops featuring totem pole three−state outputs capable of driving highly capacitive or relatively low−impedance loads. The high−impedance third state and increased high−logic−level drive provide these flip−flops with the capability of being connected directly to and driving the bus lines in a bus organized system without need for interface or pull−up components. Up to 128 of the NTE74173 outputs may be connected to a common bus and still drive two LS TTL normalized loads. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. Gated enable inputs are provided for controlling the entry of data into the flip−flops. When both data−enable inputs are low, data at the D inputs are loaded into their respective flip−flops on the next positive transition of the buffered clock input. Gate output control inputs are also provided. When both are low, the normal logic states (high or low levels) of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high-logic level at either output control input. The outputs then present a high-impedance and neither load nor drive the bus line. Detailed operation is given in the function table.

  • 3−state outputs interface directly with system bus
  • Gated output−control lines for enabling or disabling the outputs
  • Fully independent clock virtually eliminates restrictions for operating in one or two modes:
  • Parallel load
    Do nothing (hold)
  • For applications as a bus buffer register
Pricing and availability: Please note that all prices are subject to change without prior notice. Prices advertised on this site are for online orders only. Prices on some items may differ from those advertised in RadioShack stores. All merchandise may not be available at all stores, and all stores may not participate in all sales promotions. We recommend you contact the store to confirm product availability and price.

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