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NTE74166 IC TTL Shift Register

Model:

NTE74166

 | Catalog #: 55051326
Price:
$4.01
$4.01
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  • Absolute Maximum Ratings:
  • Supply voltage VCC: 7V
  • DC Input voltage VIN: 5.5V
  • Power dissipation PD: 38mW
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: −65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND

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  • Parallel load
    Do nothing (hold)
  • For applications as a bus buffer register

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  • Absolute Maximum Ratings:
    Unless otherwise specified, all voltages are referenced to GND
  • Supply voltage, VCC: 7V
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  • Output voltage (maximum applied to any output in the off state), VO: 15V
  • Operating temperature range, TA: 0°C to +70°C
  • Storage temperature range, Tstg: −65°C to +150°C

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  • Absolute maximum ratings:
  • Supply voltage VCC: 7V
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  • Power dissipation PD: 210mW
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: −65°C to +150°C

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  • Supply voltage VCC: 7V
  • DC Input voltage VIN: 5.5V
  • Power dissipation PD: 21mW
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: −65°C to +150°C
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  • Absolute maximum ratings:
  • Supply voltage VCC: 7V
  • DC Input voltage VIN: 5.5V
  • Interemitter voltage (Note 2): 5.5V
  • Power dissipation PD: 305mW
  • Operating temperature range TA: 0°C to +70°C
  • Storage temperature range Tstg: −65°C to +150°C

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Product Summary

The NTE74166 is an 8−bit parallel−in or serial−in, serial−out shift register in a 16−lead plastic DIP-type package having the complexity of 77 equivalent gates on a monolithic chip. The parallel−in or serial−in modes are established by the shift/load input. When high, this input enables the serial data input and couples the eight flip−flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low−to−high−level edge of the clock pulse through a two−input positive NOR gate permitting one input to be used as a clock enable or clock inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This, of course, allows the system clock to be free running and the register can be stopped on command with the other clock input. The clock inhibit input should be changed to the high level only while the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock and sets all flip−flops to zero. The NTE74166 is compatible with most other TTL logic families and all inputs are buffered to lower the drive requirements to one LS TTL standard load. Input clamping diodes minimize switching transients and simplify system design.

  • Synchronous load
  • Direct overriding clear
  • Parallel−to−serial conversion
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