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NTE74LS174 IC-TTL Hex D-Type Flip−Flop with Clear

Model:

NTE74LS174

 | Catalog #: 55051083
Price:
$3.45
$3.45
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  • 3−state outputs interface directly with system bus
  • Gated output−control lines for enabling or disabling the outputs
  • Independent clock virtually eliminates restrictions for operating in Parallel load or Hold
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  • Separate read/write addressing permits simultaneous reading and writing
  • Fast access time: 20ns (Typ)
  • Organized as 4 words of 4-bits
  • Expandable to 1024 words of n−bits

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  • Low-power dissipation: 100mW (Typ)
  • High−speed count frequency: 30MHz (Typ)
  • Fully synchronous operation
  • Full carry look ahead for easy cascading
  • Single up/down control input
  • Positive-edge trigger operation
  • Input clamp diodes limit high−speed termination effects
  • Absolute maximum ratings:
    VCC: 7V
  • VIN: 7V
  • TA: 0°C to +70°C
  • Tstg: −65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND

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  • Low-power dissipation: 100mW (Typ)
  • High−speed count frequency: 30MHz (Typ)
  • Fully synchronous operation
  • Full carry look ahead for easy cascading
  • Single up/down control input
  • Positive-edge trigger operation
  • Input clamp diodes limit high−speed termination effects
  • Absolute maximum ratings:
    VCC: 7V
  • VIN: 7V
  • TA: 0°C to +70°C
  • Tstg: −65°C to +150°C
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  • Synchronous load
  • Direct overriding clear
  • Parallel−to−serial conversion
  • Absolute maximum ratings:
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  • Power dissipation, PD: 100mW
  • Operating temperature range, TA: 0°C to +70°C
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  • Complementary outputs
  • Direct overriding load (data) inputs
  • Gated clock inputs
  • Parallel−to−serial data conversion
  • Absolute maximum ratings:
    VCC: 7V
  • VIN: 7V
  • PD: 10mW
  • TA: 0°C to +70°C
  • Tstg: −65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND

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Product Summary

The NTE74LS174 is a monolithic, positive−edge−triggered flip−flop in a 16−Lead plastic DIP-type package that utilizes TTL circuitry to implement D−type flip−flop logic. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive−going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive−going pulse. When the clock input is at either the high- or low-level, the D input signal have no effect at the output.

  • Contains six flip−flops with single rail outputs
  • Buffered clock and direct clear inputs
  • Individual data input to each flip−flop
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