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The NTE74LS170 is a 4−by−4 register with open collector outputs in a 16−Lead plastic DIP-type package incorporating the equivalent of 98 gates. The register file is organized as four words of four bits each and separate on−chip decoding is provided for addressing the four word locations to either write−in or retrieve data. This permits simultaneous writing into one location and reading from another word location. Four data inputs are available which are used to supply the 4−bit word to be stored. Location of the word is determined by the write−address inputs A and B in conjunction with a write−enable signal.
Data applied at the inputs should be in its true form. That is, if a high−level signal is desired from the output, a high level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write−enable input, GW, is high, the data inputs are inhibited and their levels can cause no change in the information stored in the internal latches. When the read−enable input, GR, is high, the data outputs are inhibited and remain high.
The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. When the read address is made in conjunction with the read−enable signal, the word appears at the four outputs. This arrangement -- data−entry addressing separate from data−read addressing and individual sense line -- eliminates recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time (30 nanoseconds typical) and the read time (25 nanoseconds typical).
The register file has a nondestructive readout in that data is not lost when addressed. All inputs except the read enable and write enable are buffered to lower the drive requirements to one
LS−TTL standard load. Input−clamping diodes minimize switching transients to simplify system design. High-speed, double−ended AND−OR−INVERT gates are employed for the read−address function and drive high−sink−current, open−collector outputs. Up to 256 of these outputs may be wired−AND connected for increasing the capacity up to 1024 words. Any number of these registers may be paralleled to provide n−bit word length.
Separate read/write addressing permits simultaneous reading and writing
Fast access time: 20ns (Typ)
Organized as 4 words of 4-bits
Expandable to 1024 words of n−bits
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