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The NTE74LS160A thru NTE74LS163A are synchronous, presettable counters in a 16−lead DIP-type package that feature an internal carry look ahead for application in high−speed counting designs. The NTE74LS160A and NTE74LS162A are decade counters and the NTE74LS161A and NTE74LS164A are 4−bit binary counters. Synchronous operation is provided by having all flip−flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. However, counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip−flops on the rising edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. The clear function for the NTE74LS160A and NTE74LS161A is asynchronous and a low level at the clear input sets all four of the flip−flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function of the NTE74LS162A and NTE74LS163A is synchronous and a low level at the clear input sets all four flip−flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). The carry look ahead circuitry provides for cascading counters for n−bit synchronous applications without additional gating. Instrumental in accomplishing this function are two countenable inputs and a ripple carry output. Both countenable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high−level output pulse with a duration approximately equal to the high−level portion of the Q A output. This high−level overflow ripple carry pulse can be used to enable successively cascaded stages. Transitions at the enable P or T inputs of the NTE74LS160A thru NTE74LS163A are allowed regardless of the level of the clock input. The NTE74LS160A thru NTE74LS163A feature a fully independent clock circuit. Changes at control inputs (enable P, T or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading or counting), will be dictated solely by the conditions meeting the stable setup and hold times.
Available in 4 types
Decade with direct clear: NTE74LS160A
Binary with direct clear: NTE74LS161A
Decade with synchronous clear: NTE74LS162A
Binary with synchronous clear: NTE74LS163A
Internal look ahead for fast counting
Carry output for n−bit cascading
Load control line
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