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NTE74HC74 IC TTL Dual D Flip-Flop

Model:

NTE74HC74

 | Catalog #: 55051015
Price:
$0.83
$0.83
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  • Operating voltage range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Typical propagation delay: 9ns at VCC = 5V, CL= 15pF, TA= +25°C
  • Fanout (over temp range): standard outputs 10 LS−TTL loads, bus driver outputs 15 LS-TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs

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  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Buffered inputs
  • Common 3−state output enable control
  • Bus line driving capability
  • Typical propagation delay (clock to Q): 15ns at VCC = 5V, CL = 15pF, TA = +25°C
  • Fanout (over temp range):Std outputs: 10 LS−TTL loads
    Bus driver outputs: 15 LS−TTL loads
  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • IIK, IOK: &plusnm;20mA
  • DC drain current (per output), IOUT: &plusnm;35mA
  • DC output source or sink current (per output), IOUT: &plusnm;25mA
  • ICC: &plusnm;50mA
  • TJ: +150°C
  • Tstg: −65°C to +150°C
  • RthJA: 69°C/W
  • TL: +300°C

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  • Wide power supply range: 2V to 6V
  • 3−state outputs directly drive bus lines
  • Balanced propagation delays and transition times
  • Bus driver outputs drive up to 15 LS−TTL loads
  • Significant power reduction compared to LS−TTL logic ICs
  • Absolute maximum ratings:
    VCC: −0.5 to +7.0V
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  • ICC: &plusnm;50mA
  • TJ: +150°C
  • Tstg: −65°C to +150°C
  • RthJA: 69°C/W
  • TL: +300°C

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  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Onboard oscillator
  • Common reset
  • Negative−edge clocking
  • Fanout (over temp range):
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    Bus driver outputs: 15 LS−TTL loads
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  • Significant power reduction compared to LS−TTL logic ICs
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    VCC: −0.5 to +7.0V
  • IIK, IOK: &plusnm;20mA
  • IOUT: &plusnm;25mA
  • ICC: &plusnm;50mA
  • TJ: +150°C
  • Tstg: −65°C to +150°C
  • RthJA: 67°C/W
  • TL: +300°C

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  • Wide power supply range: 2V to 6V
  • Switch voltage: 0V to 10V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Wide analog input voltage range: &plusnm;5V Max
  • Low "ON" Resistance:
    70Ω Typical (VCC − VEE = 4.5V)
    40Ω Typical (VCC − VEE = 9V)
  • Low crosstalk between switches
  • Fast switching and propagation speeds
  • "Break−before−make" switching
  • Absolute maximum ratings:*
    VCC − VEE: −0.5 to +10.5V
  • VCC: −0.5 to +7.0V
  • VEE: +0.5 to −7.0V
  • IIK: &plusnm;20mA
  • IOK: &plusnm;20mA
  • IOUT: &plusnm;25mA
  • ICC: &plusnm;50mA

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  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Fully static operation
  • Buffered inputs
  • Common reset
  • Negative edge clocking
  • Fanout (over temp. range):
    Std. outputs: 10 LS−TTL loads
    Bus driver outputs: 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • IIK, IOK: &plusnm;20mA
  • DC output source or sink current (per output), IOUT: &plusnm;25mA
  • DC VCC or GND current (per pin), ICC: &plusnm;50mA
  • TJ: +150°C
  • Tstg: −65°C to +150°C
  • RthJA: 67°C/W
  • TL: +300°C

See Full Product Description

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Availability:

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Product Summary

The NTE74HC74 is a dual D−type flip−flop in a 14−lead DIP-type package that utilizes silicon gate CMOS technology to achieve operating speeds similar to LS−TTL gates with the low-power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LS−TTL loads. This flip−flop has independent DATA, SET, RESET and CLOCK inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive−going transition of the clock pulse. SET and RESET are independent of the clock and are accomplished by a low level at the appropriate input.

  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Hysteresis on clock inputs for improved-noise immunity and increased input rise and fall times
  • Asynchronous set and reset
  • Complementary outputs
  • Buffered inputs
  • Typical f MAX: 50MHz at VCC = 5V, CL = 15pF, TA = +25°C
  • Fanout (over temp range): standard outputs 10 LS−TTL loads, bus driver outputs 15 LS-TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
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