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The NTE74HC373 is an octal transparent D−type latch in a 20−lead DIP-type package. When the latch−enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are
latched at the logic levels of the D inputs.
A buffered output−enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high−impedance state. In the high−impedance state, the outputs neither load nor drive the bus lines significantly. The high−impedance state and increased drive provide the capability
to drive bus lines without interface or pull-up components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high−impedance state.
To ensure the high−impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current−sinking capability
of the driver.
Wide power supply range: 2V to 6V
Balanced propagation delay and transition times
Standard output drives up to 15 LS−TTL loads
Significant power reduction compared to LS−TTL logic ICs
Absolute maximum ratings*: VCC: −0.5 to +7.0V
IIK, IOK: &plusnm;20mA
Drain current (per output), IOUT: &plusnm;35mA
DC output source or sink current (per output), IOUT: &plusnm;25mA
DC VCC or GND current (per pin), ICC: &plusnm;50mA
Tstg: −65°C to +150°C
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* Absolute Maximum Ratings are those values beyond which damage to the device may occur. Unless otherwise specified, all voltages are referenced to GND.