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The NTE74HC173 is a high-speed 3−state quad D−type flip−flop in a 16−Lead DIP-type package that utilizes advanced silicon−gate CMOS technology. It possesses the low-power consumption and high-noise immunity of standard CMOS integrated circuits and can operate at speeds comparable to the equivalent low-power Schottky device. The outputs are buffered, allowing this circuit to drive 15 LS−TTL loads. The large output drive capability and the 3−state feature make this part ideally suited for interfacing with bus lines in a bus-oriented system. The four D−type flip−flops operate synchronously from a common clock. The 3−state outputs allow the device to be used in bus-organized systems. The outputs are placed in the 3−state mode when
either of the two output disable pins are in the logic "1" level. The input disable allows the flip−flops to remain in their present states without having to disrupt the clock. If either of the two input disables are taken to a logic "1" level, the Q outputs are fed back to the inputs forcing the flip−flops to remain in the same state. Clearing is enabled by taking the CLEAR input to a logic "1" level. The data outputs change state on the positive going edge of the clock.
The 74HC logic family is functionally as well as pin−out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by diodes to VCC and GND.
Features: Typical propagation delay: 18ns Wide power supply range: 2V to 6V 3−state outputs Low-input current: 1µA (max) Low quiescent current: 80µA (max) High output-drive current: 6mA (min)
Absolute maximum ratings:* VCC: −0.5 to +7.0V
VIN: −1.5 to VCC +1.5V
VOUT: −0.5 to VCC + 0.5V
IIK, IOKL ±20mA
Per-pin IOUT: ±35mA
Tstg: −65°C to +150°C
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* Absolute Maximum Ratings are those values beyond which damage to the device may occur. Unless otherwise specified, all voltages are referenced to GND. Power Dissipation temperature derating: 12mW/°C from +65°C to +85°C.