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NTE74HC173 IC High-Speed CMOS Flip-Flop

Model:

NTE74HC173

 | Catalog #: 55050992
Price:
$1.70
$1.70
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  • Absolute maximum ratings:*
    -.5-7.0V
  • VIN: −1.5 to VCC +1.5V
  • VOUT: −0.5 to VCC + 0.5V
  • IIK, IOK: &plusnm;20mA
  • IOUT: &plusnm;25mA
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  • PD: 600mW
  • Tstg: −65ÜC to +150°C
  • TL: +260°C

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  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • VIN: −1.5 to VCC +1.5V
  • VOUT: −0.5 to VCC + 0.5V
  • IIK, IOK: &plusnm;20mA
  • IOUT: &plusnm;25mA
  • Per-pin ICC: &plusnm;50mA
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  • TL: +260°C

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  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • VIN: −1.5 to VCC +1.5V
  • VOUT: −0.5 to VCC + 0.5V
  • IIK, IOK: &plusnm;20mA
  • IOUT: &plusnm;25mA
  • ICC: &plusnm;50mA
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  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • IIK, IOK: &plusnm;20mA
  • Per output IOUT: &plusnm;35mA
  • Sink current per output: &plusnm;25mA
  • ICC: &plusnm;70mA
  • Tj: +150°C
  • Tstg: −65°C to +150°C
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  • TL: +300°C

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  • Typical propagation delay: 8ns
  • Wide-power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • 3−state outputs
  • Buffered inputs
  • High−current BUS driver outputs
  • Fanout (over temp range): standard outputs 10 LS−TTL loads, BUS driver outputs 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs

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Availability:

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Product Summary

The NTE74HC173 is a high-speed 3−state quad D−type flip−flop in a 16−Lead DIP-type package that utilizes advanced silicon−gate CMOS technology. It possesses the low-power consumption and high-noise immunity of standard CMOS integrated circuits and can operate at speeds comparable to the equivalent low-power Schottky device. The outputs are buffered, allowing this circuit to drive 15 LS−TTL loads. The large output drive capability and the 3−state feature make this part ideally suited for interfacing with bus lines in a bus-oriented system. The four D−type flip−flops operate synchronously from a common clock. The 3−state outputs allow the device to be used in bus-organized systems. The outputs are placed in the 3−state mode when either of the two output disable pins are in the logic "1" level. The input disable allows the flip−flops to remain in their present states without having to disrupt the clock. If either of the two input disables are taken to a logic "1" level, the Q outputs are fed back to the inputs forcing the flip−flops to remain in the same state. Clearing is enabled by taking the CLEAR input to a logic "1" level. The data outputs change state on the positive going edge of the clock. The 74HC logic family is functionally as well as pin−out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by diodes to VCC and GND. Features:
Typical propagation delay: 18ns
Wide power supply range: 2V to 6V
3−state outputs
Low-input current: 1°A (max)
Low quiescent current: 80°A (max)
High output-drive current: 6mA (min)

  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • VIN: −1.5 to VCC +1.5V
  • VOUT: −0.5 to VCC + 0.5V
  • IIK, IOKL &plusnm;20mA
  • Per-pin IOUT: &plusnm;35mA
  • ICC: &plusnm;70mA
  • PD: 600mW
  • Tstg: −65°C to +150°C
  • TL: +260°C
Pricing and availability: Please note that all prices are subject to change without prior notice. Prices advertised on this site are for online orders only. Prices on some items may differ from those advertised in RadioShack stores. All merchandise may not be available at all stores, and all stores may not participate in all sales promotions. We recommend you contact the store to confirm product availability and price.

Disclaimer: * Absolute Maximum Ratings are those values beyond which damage to the device may occur. Unless otherwise specified, all voltages are referenced to GND. Power Dissipation temperature derating: 12mW/°C from +65°C to +85°C.

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