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NTE74H78 IC TTL High-Speed M/S Flip-Flop

Model:

NTE74H78

 | Catalog #: 55050970
Price:
$2.19
$2.19
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  • Recommended operating conditions:
    VCC: 4.75-5.25VDC, 5.0VDC Typ
  • TA: 0-70°C, 25°C Typ
  • Fan out from each output: 12.5U.L.
  • tp(clock): 12ns Min
  • tp(preset): 16ns Min
  • tp(clear): 16ns Min
  • tsetup: ≥ tp(clock)
  • thold: 0

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  • Recommended operating conditions:
    VCC: 4.5-5.5VDC
  • TA: 0-70°C, 25°C Typ
  • Fan out from each output, LOW level: 12.5U.L.
  • Fan out from each output, HIGH level: 25U.L.
  • fclock: 35MHz
  • tpw(clock): 15ns Min
  • tpw(preset): 25ns Min
  • tpw(clear): 25ns Min
  • HIGH level data tsetup: 10ns Min
  • LOW level data tsetup: 15ns Min
  • thold: 0

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  • Recommended operating conditions:
    VCC: 4.5-5.5VDC
  • TA: 0-70°C, 25°C Typ
  • Fan out from each output: 12.5U.L.
  • tp(clock): 12ns min
  • tp(preset): 16ns min
  • tsetup: ≥ tp(clock)
  • thold: 0

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ONLINE In stock
Usually ships in 1 - 2 business days


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  • Recommended operating conditions:
    VCC: 4.5-+5.5VDC
  • TA: 0-70°C, 25°C Typ
  • Fan out from each output: 12.5U.L.
  • tp(clock): 12ns min
  • tp(preset): 16ns min
  • tsetup: ≥tp(clock)
  • thold: 2

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  • Recommended operating conditions:
    VCC: 4.5-5.5VDC
  • TA: 0-70°C, 25°C Typ
  • Fan out from each output: 12.5U.L.
  • tp(clock): 12ns min
  • p(preset): 16ns min
  • tsetup: ≥tp(clock)
  • thold: 0

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  • Recommended operating conditions:
    VCC: 4.75-5.25VDC, 5.0VDC Typ
  • TA: 0-70°C, 25°C Typ
  • Maximum number of expanders that may be fanned into one expander AND/OR invert gate is one

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Availability:

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Product Summary

The NTE74H78 is a high-speed dual J−K master/slave flip−flop with separate presets, a common clear and common clock in a 14−Lead DIP-type package. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the circuitry which connects the master and slave sections.
The sequence of operation is as follows:
1) Isolate slave from master
2) Enter information from J and K inputs to master
3) Disable J and K inputs
4) Transfer information from master to slave

Logic state of J and K inputs must not be allowed to change when the clock pulse is a HIGH state.

  • Recommended operating conditions:
    VCC: 4.75-5.25VDC, 5.0VDC Typ
  • TA: 0-70°, 25° Typ
  • Fan out from each output: 12.5U.L.
  • tp(clock): 12ns Min
  • tp(preset): 16ns Min
  • tp(clear): 16ns Min
  • tsetup: ≥ tp(clock)
  • thold: 0
Pricing and availability: Please note that all prices are subject to change without prior notice. Prices advertised on this site are for online orders only. Prices on some items may differ from those advertised in RadioShack stores. All merchandise may not be available at all stores, and all stores may not participate in all sales promotions. We recommend you contact the store to confirm product availability and price.

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