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The NTE74HC161 (Asynchronous Clear) and NTE74HC163 (Synchronous Clear) are synchronous presettable counters in a 16−Lead DIP-type package that utilize advanced silicon−gate CMOS technology and internal look−ahead carry logic for use in high-speed counting applications. They offer the high-noise immunity and low-power consumption inherent to CMOS with speeds similar to low-power Schottky TTL. All flip−flops are clocked simultaneously on the low-to-high-to-transition (positive−edge) of the CLOCK input waveform. These counters may be preset using the LOAD input. Presetting of all four flip−flops is synchronous to the rising edge of CLOCK. When LOAD is held low, counting is disabled and the data on the A, B, C and D inputs is loaded into the counter on the rising edge of CLOCK. If the load input is taken high before the positive edge of CLOCK, the count operation will be unaffected. Both of these counters may be cleared by utilizing the CLEAR input. The clear function on the NTE74HC163 counter is synchronous to the clock. That is, the counter is cleared on the positive edge of CLOCK while the clear input is held low. The NTE74HC161 counter is cleared asynchronously. When the CLEAR is taken low, the counter is cleared immediately, regardless of the CLOCK. Two active high enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are provided to enable easy cascading of counters. Both ENABLE inputs must be high to count. The ENT input also enables the RC output. When enabled, the RC outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the high level portion of the QA output. The RC output is fed to successive cascaded stages to facilitate easy implementation of N−bit counters. All inputs are protected from damage due to static discharge by diodes to VCC and GND.
Typical operating frequency: 40MHz
Typical propagation delay: clock to Q: 18ns
Low quiescent current: 80μA (max)
Low input current: 1μA (max)
Wide power supply range: 2V to 6V
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