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NTE NTE74HC123 IC High-Speed CMOS Multiplex

Model:

NTE74HC123

 | Catalog #: 55050978
Price:
$1.43
$1.43
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  • Recommended operating conditions:
    VCC: 4.75-5.25VDC, 5.0VDC Typ
  • TA: 0-70°, 25° Typ
  • Fan out from each output: 12.5U.L.
  • tp(clock): 12ns Min
  • tp(preset): 16ns Min
  • tp(clear): 16ns Min
  • tsetup: ≥ tp(clock)
  • thold: 0

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  • Asynchronous set and reset
  • Schmitt trigger clock inputs
  • Typical propagation delay: 18ns (typ)
  • Fanout (over temp range): standard outputs 10 LS−TTL loads, bus driver outputs 15 LS−TTL loads
  • Balanced propagation delay and transition times
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  • Typical propagation delay: 8ns (typ)
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  • Output drive capability: 10 LSTTL loads
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  • Output drive capability: 10 LSTTL loads
  • Outputs directly interface to CMOS, NMOS and TTL
  • Operating voltage range: 2V to 6V
  • Low input current: 1.0μA
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  • Buffered inputs
  • Typical propagation delay: 8ns (typ)
  • Fanout (over temp range): standard outputs 10 LS−TTL loads, bus driver outputs 15 LS−TTL loads
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Product Summary

The NTE74HC123 is a dual monostable multivibrator with resets in a 16−lead plastic DIP-type package triggered by a negative to positive reset pulse. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the A and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses. Once triggered, the output pulse width may be extended by retriggering inputs A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A) and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used, each input on the unused device (A, B, and R) must be terminated high or low. The minimum value of external resistance, RX, is typically 5kΩ. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.45 RXCX at VCC = 5V.

  • Overriding reset terminates output pulse
  • Triggering from the leading or trailing edge
  • Q and Q buffered outputs
  • Separate resets
  • Wide range of output pulse widths
  • Schmitt trigger on both A and B inputs
  • Fanout (over temp range): standard outputs 10 LS−TTL loads, bus driver outputs 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
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