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NTE NTE40193B IC-CMOS Presettable Up/Down Counters

Model:

NTE40193B

 | Catalog #: 55050792
Sale Price:
$2.52
You save:
$2.37 (48%)
 
Valid until: 07/25/14
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  • Individual clock lines for counting up or counting down
  • Synchronous high−speed carry and borrow propagation delays for cascading
  • Asynchronous reset and preset capability
  • Medium−speed operation: fCL = 8Mhz (TYP0 at 10V)
  • 5V, 10V and 15V parametric ratings
  • Standardized, symmetrical output characteristics
  • Maximum input current of 1μA at 18V over full package temperature range: 100nA at 18V and +25°C
  • Noise Margin (over full temperature range): 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V

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  • Medium−speed operation: fCL = 12Mhz (TYP) at VDD = 10V
  • Full static operation
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  • Asynchronous master reset
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  • Lightweight
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  • Fully static operation
  • Diode protection on all inputs
  • Supply voltage range: 3VDC to 18VDC
  • Capable of driving two low−power TTL loads or one low−power Schottky TTL load over the rated temp
  • Buffered outputs available from stages 1 and 4 through 14
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Product Summary

The NTE40192B (BCD Type) and NTE40193B (Binary Type) are presettable up/down counters in a 16−Lead DIP type package consisting of 4 synchronously clocked, gated "D" type flip−flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET ENABLE control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY and BORROW outputs for multiple−stage counting schemes are provided. The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET ENABLE control is low. The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down one count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high. The CARRY and BORROW signals are high when the counter is counting up or down. The CARRY signal goes low one−half clock cycle after the counter reaches its maximum count in the count−up mode. The BORROW signal goes low one−half clock cycle after the counter reaches its minimum count in the count−down mode. Cascading of multiple packages is easily accomplished without the need for additional external circuitry by tying the BORROW and CARRY outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding counter package.

  • Individual clock lines for counting up or counting down
  • Synchronous high−speed carry and borrow propagation delays for cascading
  • Asynchronous reset and preset capability
  • Medium−speed operation: fCL = 8Mhz (TYP0 at 10V)
  • 5V, 10V and 15V parametric ratings
  • Standardized, symmetrical output characteristics
  • Maximum input current of 1μA at 18V over full package temperature range: 100nA at 18V and +25°C
  • Noise margin (over full temperature range): 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
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