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NTE NTE4015B IC-CMOS Dual 4−Bit Static Shift Register

Model:

NTE4015B

 | Catalog #: 55050779
Price:
$4.08
$4.08
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  • Synchronous parallel input/serial output
  • Synchronous serial output/serial output
  • Full static operation
  • "Q" outputs from sixth, seventh and eighth stages
  • Double diode input protection
  • Supply voltage range: 3VDC to 18VDC
  • Capable of driving two low−power TTL loads or one low−power Schottky TTL load over the rated temp

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  • Supply voltage range: 3V to 15V
  • High noise immunity: 0.45VDD Typ
  • Diode protection on all inputs
  • Capable of driving two low-power TTL loads
  • Operating ambient temperature range: −55° to +125°C
  • Storage temperature: −65° to +150°C

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  • Supply voltage range: 3V to 15V
  • High noise immunity: 0.45VDD Typ
  • Diode protection on all inputs
  • Capable of driving two low-power TTL loads
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  • Supply voltage range: 3VDC to 18VDC
  • All outputs buffered
  • Capable of driving two low−power TTL loads or one low−power Schottky TTL load over the rated temp
  • Double diode protection on all inputs

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  • Supply voltage range: 3VDC to 18VDC
  • All outputs buffered
  • Capable of driving two low−power TTL loads or one low−power Schottky TTL load over the rated temp
  • Double diode protection on all inputs

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  • Supply voltage range: 3VDC to 18VDC
  • All outputs buffered
  • Capable of driving two low−power TTL loads or one low−power Schottky TTL load over the rated temp
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Product Summary

The NTE4015B (16−Lead DIP) and NTE4015BT (SOIC−16) are dual 4−bit static shift registers constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These devices consist of two identical, independent 4−state serial−input/parallel−output registers. Each register has independent clock and reset inputs with a single serial data input. The register states are type D master−slave flip−flops. Data is shifted from one stage to the next during the positive−going clock transition. Each register can be cleared when a high level is applied on the reset line. These complementary MOS shift registers find primary use in buffer storage and serial−to−parallel conversion where low-power dissipation and/or noise-immunity is desired.

  • Diode protection on all inputs
  • Supply voltage range: 3VDC to 18VDC
  • Logic edge−clocked flip−flop design
  • Logic state is retained indefinitely with clock level either high or low
  • Information is transferred to the output only on the positive going edge of the clock pulse
  • Capable of driving two low−power TTL loads or one low−power Schottky TTL load over the rated temp
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