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The NTE4518B (16−lead DIP) and NTE4518BT (SOIC−16) are dual BCD up counters constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each consists of two identical, independent, internally synchronous 4−stage counters. The counter stages are type D flip−flops, with interchangeable Clock and Enable lines for incrementing on either the positive−
going or negative−going transition as required when cascading multiple stages. Each counter can be cleared by applying a high level on the Reset line. In addition, the NTE4518B/BT will count out of all undefined states within two clock periods. These complementary MOS up counters find primary use in multistage synchronous or ripple counting applications requiring low-power dissipation and/or high-noise immunity.
VDD = −0.5 to +18.0V
Vin = −0.5 to VDD + 0.5V
I (per pin) = 10mA
TA = −55 to +125°C
Tstg = −65 to +150°C
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These devices contain circuitry to protect the inputs against damage due to high static voltage or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) VDD.