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The NTE4508B is a dual 4−bit latch in a 24−lead DIP-type package constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. The part consists of two identical, independent 4−bit latches with separate Strobe (ST) and Master Reset (MR) controls. Separate Disable inputs force the outputs to a high impedance state and allow the devices to be used in time-sharing bus-line applications. These complementary MOS latches find primary use in buffer storage, holding register, or general digital logic functions where low-power dissipation and/or high-noise immunity is desired.
VDD = −0.5 to +18.0V
Vin = −0.5 to VDD to +0.5V
I (per pin) = 0mA
TA = −55° to +125°C
Tstg = −65° to +150°C
Above are maximum ratings, those values beyond which damage to the device may occur
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This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that V9in9 and V9out9 be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic level (e.g., either VSS or VDD).