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The NTE4096B is a J−K Master−Slave Flip−Flop in a 14−lead DIP-type package featuring separate AND gating of multiple J and K inputs. The gated J−K inputs control transfer of information into the master section during clocked operation. Information on the J−K inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse. SET and RESET inputs (active high) are provided for asynchronous operation.
VDD = −0.5 to +20V
Input voltage range, all inputs = −0.5 to VDD+0.5V
For TA = −55° to +100°C, PD = 500mW TA = +100° to +125°C = Derate Linearly at 12mW/°C to 200mW
Device dissipation (per output transistor) for TA = −55° to +125°C = 100mW
TA = −55° to +125°C
Tstg = −65° to +150°C
TL = +265°C
Above are maximum ratings that if exceeded may cause damage to the device
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