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NTE4093BT CMOS Quad 2−Input NAND Schmitt Trigger

Model:

NTE4093BT

 | Catalog #: 55050879
Price:
$0.87
$0.87
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  • VDD = −0.5 to +20V
  • Input voltage range, all inputs = −0.5 to VDD+0.5V
  • TA = −55° to +100°C, PD = 500mW
    TA = +100° to +125°C = Derate linearly at 12mW/°C to 200mW
  • Device dissipation per output transistor for TA = −55° to +125°C = 100mW
  • TA = −55° to +125°C
  • Tstg = −65° to +150°C
  • TL = +265°C
  • Above are maximum ratings which if exceeded may damage the device

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  • Dimensions (LxHxW): 0.766x0.422x0.422"

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  • Full auto-ranging with manual range override
  • Diode and transistor modes and continuity check with beeper
  • Relative and logic modes
  • AC voltage display mode
  • Unit has auto polarity, data hold, low battery indicator, and overload indicator
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Product Summary

The NTE4093B (14−lead DIP) and NTE4093BT (SOIC−14) Schmitt Triggers are constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These devices find primary use where low-power dissipation and/or high-noise immunity is desired. The NTE4093B/BT may be used in place of the NTE4011B/BT quad 2−input NAND gate for enhanced noise immunity or to "square up" slowly changing waveforms.

  • VDD = −0.5 to +18.0V
  • Vin = −0.5 to VDD + 0.5V
  • I = 10mA
  • TA = −55 to +125°C
  • Tstg = −65 to +150°C
Pricing and availability: Please note that all prices are subject to change without prior notice. Prices advertised on this site are for online orders only. Prices on some items may differ from those advertised in RadioShack stores. All merchandise may not be available at all stores, and all stores may not participate in all sales promotions. We recommend you contact the store to confirm product availability and price.

Disclaimer: These devices contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤(Vin or Vout) ≤VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).

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