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The NTE4076B is a 4−bit register in a 16−lead DIP-type package consisting of four D−type flip−flops operating synchronously from a common clock. OR gated output−disable inputs force the outputs into a high−impedance state for use in bus organized systems. OR gated data−disable inputs cause the Q outputs to be fed back to the D inputs of the flip−flops. Thus, they are inhibited from hanging state while the clocking process remains undisturbed. An asynchronous master reset is provided to clear all four flip−flops simultaneously independent of the clock or disable inputs.
VDD = −0.5 to +18.0V
Vin = −0.5 to VDD + 0.5V
I = 10mA
TsA = −55 to +125°C
Tstg = −65 to +150°C
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These devices contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤(Vin or Vout) ≤VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).