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The NTE4035B is a 4−bit shift register in a 16−lead DIP type package constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. It consists of a 4−stage clocked serial−shift register with synchronous parallel inputs and buffered parallel outputs. The parallel/serial (P/S) input allows serial−right shifting of data or synchronous parallel loading via inputs DP0 through DP3. The true/complement (T/C) input determines whether the outputs display the Q or Q outputs of the flip−flop stages. J−K logic forms the serial input to the first stage. With the J and K inputs connected together they operate as a serial "D" input.
VDD = −0.5 to +18.0V
VIN = −0.5 to VDD +0.5V
VOUT = −0.5 to VDD +0.5V
IIN = &plusnm;10mA
IOUT = &plusnm;10mA
PD = 500mW Temperature derating (from +65° to +125°C) = −7.0mW/°C
Tstg = −65° to +150°C
TL = +260°C
Above are maximum ratings - those values beyond which damage to the device may occur
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