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The NTE4031B is an integrated, complementary MOS, 64−stage fully static shift register in a 16−lead DIP package. Two data inputs, DATA IN and RECIRCULATE IN, and a MODE CONTROL input are provided. Data at the DATA input (when MODE CONTROL is low) or data at the RECIRCULATE input (when MODE CONTROL is high), which meets the setup and hold time requirements, is entered into the first stage of the register and is shifted one stage at each positive transition of the CLOCK. Data output is available in both true and complement forms from the 64th stage. Both DATA OUT (Q) outputs are fully buffered. The CLOCK input of the NTE4031B is fully buffered and presents only a standard input load capacitance. However, a DELAYED CLOCK OUTPUT (CLD) has been provided to allow reduced clock drive fan−out and transition time requirements when cascading packages.
Wide supply voltage range: 3VDC to 18VDC
High noise immunity: 0.45 VDD (typical)
Low power TTL compatibility: fan out of 2 driving 74L or one driving 74LS
Fully static operation: DC to 8MHz, VDD = 10V (typical)
High current sinking capability: 1.6mA at VDD = 5V and +25°C
Supply voltage, VDD: −0.5 to +18.0V
Input voltage, VIN: −0.5 to VDD +0.5V
Power dissipation, PD: 500mW
Storage temperature range, Tstg: −65° to +150°C
Lead temperature (during Soldering, 10sec max), TL: +260°C
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