• Model: NTE74LS166
  • Catalog #: 55051078

NTE74LS166 IC TTL 8−Bit Shift Register

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$1.22

In Stock

(Online Only)

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE74LS166 is an 8−bit parallel−in or serial−in, serial−out shift register in a 16−Lead plastic DIP-type package having the complexity of 77 equivalent gates on a monolithic chip. The parallel−in or serial−in modes are established by the shift/load input. When high, this input enables the serial data input and couples the eight flip−flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low−to−high−level edge of the clock pulse through a two−input positive NOR gate permitting one input to be used as a clock enable or clock−inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This, of course, allows the system clock to be free−running and the register can be stopped on command with the other clock input. The clock inhibit input should be changed to the high level only while the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip−flops to zero. The NTE74LS166 is compatible with most other TTL logic families and all inputs are buffered to lower the drive requirements to one LS−TTL standard load. Input clamping diodes minimize switching transients and simplify system design.
  • Synchronous load
  • Direct overriding clear
  • Parallel−to−serial conversion
  • Absolute maximum ratings:
    Supply voltage, VCC: 7V
  • DC input voltage, VIN: 7V
  • Power dissipation, PD: 100mW
  • Operating temperature range, TA: 0°C to +70°C
  • Storage temperature range, Tstg: −65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND
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Shipping

Ships in 1-2 Business Days

Presentation Attributes

Storefront Attributes

Search Refinements

Shop Runner

Battery Features

Capacity UOM

mAh

Rechargeable

No

Cleansing

Dimensions

Fulfillment

Package Height

0.50

Package Length

6.25

Package Width

3.70

General

Model

NTE74LS166

Product Type

Registers and buffers

Identification

Manufacturer Part Number

NTE74LS166

Surcharge

Legal

Merchandising

Inputs & Outputs

Miscellaneous Features

Operating Temperature UOM

° F

Supported Languages

English

Power Features

Docking station

No

Promo

Retail

Price

Remote Control Features

Warranty

0.00

0.00

Available RadioShack Service Plan

No

Warranty Labor UOM

days

Warranty Parts UOM

days

Root

Additional Features

Water-Resistant or Waterproofness Standard

No

Miscellaneous Features

Power Features

Print
 

Summary

The NTE74LS166 is an 8−bit parallel−in or serial−in, serial−out shift register in a 16−Lead plastic DIP-type package having the complexity of 77 equivalent gates on a monolithic chip. The parallel−in or serial−in modes are established by the shift/load input. When high, this input enables the serial data input and couples the eight flip−flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low−to−high−level edge of the clock pulse through a two−input positive NOR gate permitting one input to be used as a clock enable or clock−inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This, of course, allows the system clock to be free−running and the register can be stopped on command with the other clock input. The clock inhibit input should be changed to the high level only while the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip−flops to zero. The NTE74LS166 is compatible with most other TTL logic families and all inputs are buffered to lower the drive requirements to one LS−TTL standard load. Input clamping diodes minimize switching transients and simplify system design.
  • Synchronous load
  • Direct overriding clear
  • Parallel−to−serial conversion
  • Absolute maximum ratings:
    Supply voltage, VCC: 7V
  • DC input voltage, VIN: 7V
  • Power dissipation, PD: 100mW
  • Operating temperature range, TA: 0°C to +70°C
  • Storage temperature range, Tstg: −65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND

Tech Specs

The NTE74LS166 is an 8−bit parallel−in or serial−in, serial−out shift register in a 16−Lead plastic DIP-type package having the complexity of 77 equivalent gates on a monolithic chip. The parallel−in or serial−in modes are established by the shift/load input. When high, this input enables the serial data input and couples the eight flip−flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low−to−high−level edge of the clock pulse through a two−input positive NOR gate permitting one input to be used as a clock enable or clock−inhibit function. Holding either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This, of course, allows the system clock to be free−running and the register can be stopped on command with the other clock input. The clock inhibit input should be changed to the high level only while the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip−flops to zero. The NTE74LS166 is compatible with most other TTL logic families and all inputs are buffered to lower the drive requirements to one LS−TTL standard load. Input clamping diodes minimize switching transients and simplify system design.

Reviews

$ $1.22 In Stock