• Model: NTE74LS165
  • Catalog #: 55051077

NTE74LS165 IC TTL 8-Bit Shift Register

Details

$2.59

In Stock

(Online Only)

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE74LS165 is an 8−bit serial shift register in a 16−Lead plastic DIP-type package that shifts the data in the direction of QA toward QH when clocked. Parallel−in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift/load input. This register also features gated clock inputs and complementary outputs from the eighth bit. All inputs are diode−clamped to minimize transmission−line effects, thereby simplifying system design. Clocking is accomplished through a 2−input positive−NOR gate, permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift/load input high enables the other clock input. The clock inhibit input should be changed to the high level only while the clock input is high. Parallel loading is inhibited as long as the shift/load input is high. Data at the parallel inputs are loaded directly into the register while the shift/load input is low independently of the levels of the clock, clock inhibit, or serial inputs.
  • Complementary outputs
  • Direct overriding load (data) inputs
  • Gated clock inputs
  • Parallel−to−serial data conversion
  • Absolute maximum ratings:
    VCC: 7V
  • VIN: 7V
  • PD: 10mW
  • TA: 0°C to +70°C
  • Tstg: −65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND
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Shipping

Ships in 1-2 Business Days

Presentation Attributes

Storefront Attributes

Search Refinements

Shop Runner

Battery Features

Capacity UOM

mAh

Rechargeable

No

Cleansing

Dimensions

Fulfillment

Package Height

0.50

Package Length

6.25

Package Width

3.70

General

Model

NTE74LS165

Product Type

Registers and buffers

Identification

Manufacturer Part Number

NTE74LS165

Surcharge

Legal

Merchandising

Inputs & Outputs

Miscellaneous Features

Operating Temperature UOM

° F

Supported Languages

English

Power Features

Docking station

No

Promo

Retail

Price

Remote Control Features

Warranty

0.00

0.00

Available RadioShack Service Plan

No

Warranty Labor UOM

days

Warranty Parts UOM

days

Root

Additional Features

Water-Resistant or Waterproofness Standard

No

Miscellaneous Features

Power Features

Print
 

Summary

The NTE74LS165 is an 8−bit serial shift register in a 16−Lead plastic DIP-type package that shifts the data in the direction of QA toward QH when clocked. Parallel−in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift/load input. This register also features gated clock inputs and complementary outputs from the eighth bit. All inputs are diode−clamped to minimize transmission−line effects, thereby simplifying system design. Clocking is accomplished through a 2−input positive−NOR gate, permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift/load input high enables the other clock input. The clock inhibit input should be changed to the high level only while the clock input is high. Parallel loading is inhibited as long as the shift/load input is high. Data at the parallel inputs are loaded directly into the register while the shift/load input is low independently of the levels of the clock, clock inhibit, or serial inputs.
  • Complementary outputs
  • Direct overriding load (data) inputs
  • Gated clock inputs
  • Parallel−to−serial data conversion
  • Absolute maximum ratings:
    VCC: 7V
  • VIN: 7V
  • PD: 10mW
  • TA: 0°C to +70°C
  • Tstg: −65°C to +150°C
  • Unless otherwise specified, all voltages are referenced to GND

Tech Specs

The NTE74LS165 is an 8−bit serial shift register in a 16−Lead plastic DIP-type package that shifts the data in the direction of QA toward QH when clocked. Parallel−in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift/load input. This register also features gated clock inputs and complementary outputs from the eighth bit. All inputs are diode−clamped to minimize transmission−line effects, thereby simplifying system design. Clocking is accomplished through a 2−input positive−NOR gate, permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift/load input high enables the other clock input. The clock inhibit input should be changed to the high level only while the clock input is high. Parallel loading is inhibited as long as the shift/load input is high. Data at the parallel inputs are loaded directly into the register while the shift/load input is low independently of the levels of the clock, clock inhibit, or serial inputs.

Reviews

$ $2.59 In Stock