• Model: NTE74HCT273
  • Catalog #: 55051027

NTE74HCT273 IC High-Speed CMOS Flip-Flop

Details

$1.91

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(Online Only)

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE74HC273 is a high-speed octal D−type flip−flop with a direct clear input in a 20−Lead DIP-type package manufactured with silicon−gate CMOS technology that has the low-power consumption of standard CMOS integrated circuits. Information at the D inputs is transferred to the Q outputs on the positive−going edge of the clock pulse. All eight flip−flops are controlled by common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.
  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Common clock and asynchronous master reset
  • Positive-edge triggering
  • Buffered inputs
  • Fanout (over temp rng):
    Std. outputs: 10 LS−TTL loads
    Bus driver outputs: 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • IIK, IOK: ±20mA
  • DC drain current (per output), IOUT: ±25mA
  • DC output source or sink current (per output), IOUT: ±25mA
  • DC VCC or GND current (per pin), ICC: ±50mA
  • TJ: +150°C
  • Tstg: −65°C to +150°C
  • RthJA: 69°C/W
  • TL: +300°C
* Absolute Maximum Ratings are those values beyond which damage to the device may occur. Unless otherwise specified, all voltages are referenced to GND.
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Shipping

Ships in 1-2 Business Days

Presentation Attributes

Storefront Attributes

Search Refinements

Shop Runner

Battery Features

Capacity UOM

mAh

Rechargeable

No

Cleansing

Dimensions

Fulfillment

Package Height

0.50

Package Length

6.25

Package Width

3.70

General

Model

NTE74HCT273

Product Type

Flip-flops

Identification

Manufacturer Part Number

NTE74HCT273

Surcharge

Legal

Merchandising

Inputs & Outputs

Miscellaneous Features

Operating Temperature UOM

° F

Supported Languages

English

Power Features

Docking station

No

Promo

Retail

Price

Remote Control Features

Warranty

0.00

0.00

Available RadioShack Service Plan

No

Warranty Labor UOM

days

Warranty Parts UOM

days

Root

Additional Features

Water-Resistant or Waterproofness Standard

No

Miscellaneous Features

Power Features

Print
 

Summary

The NTE74HC273 is a high-speed octal D−type flip−flop with a direct clear input in a 20−Lead DIP-type package manufactured with silicon−gate CMOS technology that has the low-power consumption of standard CMOS integrated circuits. Information at the D inputs is transferred to the Q outputs on the positive−going edge of the clock pulse. All eight flip−flops are controlled by common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.
  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Common clock and asynchronous master reset
  • Positive-edge triggering
  • Buffered inputs
  • Fanout (over temp rng):
    Std. outputs: 10 LS−TTL loads
    Bus driver outputs: 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • IIK, IOK: ±20mA
  • DC drain current (per output), IOUT: ±25mA
  • DC output source or sink current (per output), IOUT: ±25mA
  • DC VCC or GND current (per pin), ICC: ±50mA
  • TJ: +150°C
  • Tstg: −65°C to +150°C
  • RthJA: 69°C/W
  • TL: +300°C

Tech Specs

The NTE74HC273 is a high-speed octal D−type flip−flop with a direct clear input in a 20−Lead DIP-type package manufactured with silicon−gate CMOS technology that has the low-power consumption of standard CMOS integrated circuits. Information at the D inputs is transferred to the Q outputs on the positive−going edge of the clock pulse. All eight flip−flops are controlled by common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.

Reviews