• Model: NTE74HC40105
  • Catalog #: 55051008

NTE74HC40105 IC High-Speed CMOS Register

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$3.86

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(Online Only)

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE74HC40105 is a high-speed silicon gate CMOS device in a 16−Lead DIP-type package that is compatible, except for “shift−out” circuitry, with the NTE40105B. This device is a low−power first−in−out (FIFO) “elastic” storage register that can store 16 4−bit words. The NTE74HC40105 is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each work position in the register is clocked by a control flip−flop, which stores a marker bit. A “1” signifies that the position’s data is filled and a “0” denotes a vacancy in that position. The control flip−flop detects the state of the preceding flip−flop and communicates its own status to the succeeding flip−flop. When a control flip−flop is in the “0” state and sees a “1” in the preceding flip−flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip−flop to “0”. The first and last control flip−flops have buffered outputs. Since all empty locations “bubble” automatically to the input end, an all valid data ripple through to the output end, the status of the first control flip−flop (DATA−IN READY) indicates if the FIFO is full, and the status of the last flip−flop (DATA−OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.
  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Independent asynchronous inputs and outputs
  • Expandable in either direction
  • Reset capability
  • Status indicators on inputs and outputs
  • 3−state outputs
  • Shift−out independent of 3−state control
  • Fanout (over temp R): Std outputs: 10 LS−TTL loads Bus driver outputs: 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
  • Applications:
    Bit−rate smoothing
    CPU/terminal buffering
    Data communications
  • Peripheral buffering
    Line printer input buffers
    Auto−dialers
    CRT buffer memories
  • Radar data acquisition
  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • IIK, IOK: ±20mA
  • DC output source or sink current (per output), IOUT: ±25mA
  • DC VCC or GND current (per pin), ICC: ±50mA
  • TJ: +150°C
  • Tstg: −65°C to +150°C
  • RthJA: 67°C/W
  • TL: +300° C
* Absolute Maximum Ratings are those values beyond which damage to the device may occur. Unless otherwise specified, all voltages are referenced to GND.
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Presentation Attributes

Storefront Attributes

Search Refinements

Shop Runner

Battery Features

Capacity UOM

mAh

Rechargeable

No

Cleansing

Dimensions

Fulfillment

Package Height

0.50

Package Length

6.25

Package Width

3.70

General

Model

NTE74HC40105

Product Type

Registers and buffers

Identification

Manufacturer Part Number

NTE74HC40105

Surcharge

Legal

Merchandising

Inputs & Outputs

Miscellaneous Features

Operating Temperature UOM

° F

Supported Languages

English

Power Features

Docking station

No

Promo

Retail

Price

Remote Control Features

Warranty

0.00

0.00

Available RadioShack Service Plan

No

Warranty Labor UOM

days

Warranty Parts UOM

days

Root

Additional Features

Water-Resistant or Waterproofness Standard

No

Miscellaneous Features

Power Features

Print
 

Summary

The NTE74HC40105 is a high-speed silicon gate CMOS device in a 16−Lead DIP-type package that is compatible, except for “shift−out” circuitry, with the NTE40105B. This device is a low−power first−in−out (FIFO) “elastic” storage register that can store 16 4−bit words. The NTE74HC40105 is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each work position in the register is clocked by a control flip−flop, which stores a marker bit. A “1” signifies that the position’s data is filled and a “0” denotes a vacancy in that position. The control flip−flop detects the state of the preceding flip−flop and communicates its own status to the succeeding flip−flop. When a control flip−flop is in the “0” state and sees a “1” in the preceding flip−flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip−flop to “0”. The first and last control flip−flops have buffered outputs. Since all empty locations “bubble” automatically to the input end, an all valid data ripple through to the output end, the status of the first control flip−flop (DATA−IN READY) indicates if the FIFO is full, and the status of the last flip−flop (DATA−OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.
  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Independent asynchronous inputs and outputs
  • Expandable in either direction
  • Reset capability
  • Status indicators on inputs and outputs
  • 3−state outputs
  • Shift−out independent of 3−state control
  • Fanout (over temp R): Std outputs: 10 LS−TTL loads Bus driver outputs: 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
  • Applications:
    Bit−rate smoothing
    CPU/terminal buffering
    Data communications
  • Peripheral buffering
    Line printer input buffers
    Auto−dialers
    CRT buffer memories
  • Radar data acquisition
  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • IIK, IOK: ±20mA
  • DC output source or sink current (per output), IOUT: ±25mA
  • DC VCC or GND current (per pin), ICC: ±50mA
  • TJ: +150°C
  • Tstg: −65°C to +150°C
  • RthJA: 67°C/W
  • TL: +300° C

Tech Specs

The NTE74HC40105 is a high-speed silicon gate CMOS device in a 16−Lead DIP-type package that is compatible, except for “shift−out” circuitry, with the NTE40105B. This device is a low−power first−in−out (FIFO) “elastic” storage register that can store 16 4−bit words. The NTE74HC40105 is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each work position in the register is clocked by a control flip−flop, which stores a marker bit. A “1” signifies that the position’s data is filled and a “0” denotes a vacancy in that position. The control flip−flop detects the state of the preceding flip−flop and communicates its own status to the succeeding flip−flop. When a control flip−flop is in the “0” state and sees a “1” in the preceding flip−flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip−flop to “0”. The first and last control flip−flops have buffered outputs. Since all empty locations “bubble” automatically to the input end, an all valid data ripple through to the output end, the status of the first control flip−flop (DATA−IN READY) indicates if the FIFO is full, and the status of the last flip−flop (DATA−OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.

Reviews

$ $3.86 In Stock