• Model: NTE74HC390
  • Catalog #: 55051006

NTE74HC390 IC High-Speed CMOS Dual Decade Ripple Counter

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$1.51

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE74HC390 is a dual 4−bit decade ripple counter in a 16−lead DIP-type package and is pin compatible with low−power Schottky TTL (LS−TTL). This device is divided into four separately clocked sections. The counters have two divide−by−2 sections and two divide−by−5 sections. These sections are normally used in a BCD decade or biquinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide−by−2, 4, 5, 10, 20, 25, 50 or 100. Each section is triggered by the High−to−Low transition of the input pulses (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide−by−5 section. For bi−quinary decade operation, the nO3 output is connected to the nCP0 input and nQ0 becomes the decade output. The master reset inputs (1MR and 2MR) are active−High asynchronous inputs to each decade counter which operates on the portion of the counter identified by the “1” and “2” prefixes in the pin configuration. A High level on the nMR input overrides the clock and sets the four outputs Low.
  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • 2 BCD decades or biquinary counters
  • One package can be configured to divide by 2, 4, 5, 10, 20, 25, 50 or 100
  • 2 master reset inputs to clear each decade counter individually
  • Fanout (over temp. range):
    Std. outputs: 10 LS−TTL loads
    Bus driver outputs: 15 LS−TTL
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • IIK, IOK: ±20mA
  • DC output source or sink current (per output), IOUT: ±25mA
  • DC VCC or GND current (per pin), ICC: ±50mA
  • TJ: +150°C
  • Tstg: −65°C to +150°C
  • RthJA: 67°C/W
  • TL: +300°C
* Absolute Maximum Ratings are those values beyond which damage to the device may occur. Unless otherwise specified, all voltages are referenced to GND.
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Presentation Attributes

Storefront Attributes

Search Refinements

Shop Runner

Battery Features

Capacity UOM

mAh

Rechargeable

No

Cleansing

Dimensions

Fulfillment

Package Height

0.50

Package Length

6.25

Package Width

3.70

General

Model

NTE74HC390

Product Type

Counters

Identification

Manufacturer Part Number

NTE74HC390

Surcharge

Legal

Merchandising

Inputs & Outputs

Miscellaneous Features

Operating Temperature UOM

° F

Supported Languages

English

Power Features

Docking station

No

Promo

Retail

Price

Remote Control Features

Warranty

0.00

0.00

Available RadioShack Service Plan

No

Warranty Labor UOM

days

Warranty Parts UOM

days

Root

Additional Features

Water-Resistant or Waterproofness Standard

No

Miscellaneous Features

Power Features

Print
 

Summary

The NTE74HC390 is a dual 4−bit decade ripple counter in a 16−lead DIP-type package and is pin compatible with low−power Schottky TTL (LS−TTL). This device is divided into four separately clocked sections. The counters have two divide−by−2 sections and two divide−by−5 sections. These sections are normally used in a BCD decade or biquinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide−by−2, 4, 5, 10, 20, 25, 50 or 100. Each section is triggered by the High−to−Low transition of the input pulses (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide−by−5 section. For bi−quinary decade operation, the nO3 output is connected to the nCP0 input and nQ0 becomes the decade output. The master reset inputs (1MR and 2MR) are active−High asynchronous inputs to each decade counter which operates on the portion of the counter identified by the “1” and “2” prefixes in the pin configuration. A High level on the nMR input overrides the clock and sets the four outputs Low.
  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • 2 BCD decades or biquinary counters
  • One package can be configured to divide by 2, 4, 5, 10, 20, 25, 50 or 100
  • 2 master reset inputs to clear each decade counter individually
  • Fanout (over temp. range):
    Std. outputs: 10 LS−TTL loads
    Bus driver outputs: 15 LS−TTL
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
  • Absolute maximum ratings:*
    VCC: −0.5 to +7.0V
  • IIK, IOK: ±20mA
  • DC output source or sink current (per output), IOUT: ±25mA
  • DC VCC or GND current (per pin), ICC: ±50mA
  • TJ: +150°C
  • Tstg: −65°C to +150°C
  • RthJA: 67°C/W
  • TL: +300°C

Tech Specs

The NTE74HC390 is a dual 4−bit decade ripple counter in a 16−lead DIP-type package and is pin compatible with low−power Schottky TTL (LS−TTL). This device is divided into four separately clocked sections. The counters have two divide−by−2 sections and two divide−by−5 sections. These sections are normally used in a BCD decade or biquinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide−by−2, 4, 5, 10, 20, 25, 50 or 100. Each section is triggered by the High−to−Low transition of the input pulses (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide−by−5 section. For bi−quinary decade operation, the nO3 output is connected to the nCP0 input and nQ0 becomes the decade output. The master reset inputs (1MR and 2MR) are active−High asynchronous inputs to each decade counter which operates on the portion of the counter identified by the “1” and “2” prefixes in the pin configuration. A High level on the nMR input overrides the clock and sets the four outputs Low.

Reviews