• Model: NTE74HC299
  • Catalog #: 55051001

NTE74HC299 IC Hi-Speed CMOS Register

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$3.06

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE74HC299 is an 8−bit shift/storage register with three−state bus interface capability in a 20−lead DIP-type package. The register has four synchronous−operating modes controlled by two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0 − I/O7) respond only to the low−to−high transition of the clock (CP) pulse. S0, S1 and data inputs must be stable one set−up time prior to the clock positive transaction. The Master Reset (MR) is an asynchronous active low input. When MR output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.

The three−state input/output (I/O) port has three modes of operation:

1. Both output enable (OE1 and OE2) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs.

2. When both S0 and S1 are high, I/O terminals are in the high-impedance state but being input ports, ready for parallel data to be loaded into eight registers with one clock transition regardless of the status of OE1 and OE2.

3. Either one of the two output enable inputs being high will force I/O terminals to be in the off−state. It is noted that each I/O terminal is a three−state output and a CMOS buffer input.
  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Buffered inputs
  • Four operating modes: shift left, shift right, load and store
  • Can be cascaded for N−bit word lengths
  • I/O0 − I/O7 bus drive capability and three−state for bus oriented applications
  • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = +25°C
  • Fanout (over temp range): standard outputs: 10 LS−TTL loads, bus driver outputs: 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
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Presentation Attributes

Storefront Attributes

Search Refinements

Shop Runner

Custom Product Attributes

Battery Features

Capacity UOM

mAh

Rechargeable

No

Cleansing

Dimensions

Fulfillment

Package Height

0.50

Package Length

6.25

Package Width

3.70

General

Model

NTE74HC299

Product Type

Registers and buffers

Identification

Manufacturer Part Number

NTE74HC299

Surcharge

Legal

Merchandising

Inputs & Outputs

Miscellaneous Features

Operating Temperature UOM

° F

Supported Languages

English

Power Features

Docking station

No

Promo

Retail

Price

Remote Control Features

Warranty

0.00

0.00

Available RadioShack Service Plan

No

Warranty Labor UOM

days

Warranty Parts UOM

days

Root

Additional Features

Water-Resistant or Waterproofness Standard

No

Miscellaneous Features

Power Features

Print
 

Summary

The NTE74HC299 is an 8−bit shift/storage register with three−state bus interface capability in a 20−lead DIP-type package. The register has four synchronous−operating modes controlled by two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0 − I/O7) respond only to the low−to−high transition of the clock (CP) pulse. S0, S1 and data inputs must be stable one set−up time prior to the clock positive transaction. The Master Reset (MR) is an asynchronous active low input. When MR output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.

The three−state input/output (I/O) port has three modes of operation:

1. Both output enable (OE1 and OE2) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs.

2. When both S0 and S1 are high, I/O terminals are in the high-impedance state but being input ports, ready for parallel data to be loaded into eight registers with one clock transition regardless of the status of OE1 and OE2.

3. Either one of the two output enable inputs being high will force I/O terminals to be in the off−state. It is noted that each I/O terminal is a three−state output and a CMOS buffer input.
  • Wide power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Buffered inputs
  • Four operating modes: shift left, shift right, load and store
  • Can be cascaded for N−bit word lengths
  • I/O0 − I/O7 bus drive capability and three−state for bus oriented applications
  • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = +25°C
  • Fanout (over temp range): standard outputs: 10 LS−TTL loads, bus driver outputs: 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs

Tech Specs

The NTE74HC299 is an 8−bit shift/storage register with three−state bus interface capability in a 20−lead DIP-type package. The register has four synchronous−operating modes controlled by two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0 − I/O7) respond only to the low−to−high transition of the clock (CP) pulse. S0, S1 and data inputs must be stable one set−up time prior to the clock positive transaction. The Master Reset (MR) is an asynchronous active low input. When MR output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the first stage.

The three−state input/output (I/O) port has three modes of operation:

1. Both output enable (OE1 and OE2) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs.

2. When both S0 and S1 are high, I/O terminals are in the high-impedance state but being input ports, ready for parallel data to be loaded into eight registers with one clock transition regardless of the status of OE1 and OE2.

3. Either one of the two output enable inputs being high will force I/O terminals to be in the off−state. It is noted that each I/O terminal is a three−state output and a CMOS buffer input.

Reviews

$ $3.06 In Stock