• Model: NTE74HC259
  • Catalog #: 55050999

NTE74HC259 IC Hi-Speed CMOS Decoder

Details

$1.70

In Stock

(Online Only)

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE74HC259 is an 8−bit addressable latch in a 16−lead DIP-type package that features the low−power consumption associated with CMOS circuitry and has speeds comparable to low−power Schottky. This latches three active modes and one reset mode. When both the Latch Enable (LE) and Master Reset (MR) inputs are low (8−line demultiplexer mode) the output of the addressed latch follows the data input and all other outputs are forced low. When both MR and LE are high (memory mode), all outputs are isolated from the data input, i.e. all latches hold the last data presented before the LE transition from low to high. A condition of LE low and MR high (addressable latch mode) allows the addressed latch’s output to follow the data input, all other latches are unaffected. The reset mode (all outputs low) results when LE is high and MR is low.
  • Wide-power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Buffered inputs and outputs
  • Four operating modes
  • Typical propagation delay: 15ns at VCC = 5V, CL = 15pF, TA = +25°C
  • Fanout (over temp range): standard outputs 10 LS−TTL loads, bus driver outputs 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs
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Shipping

Ships in 1-2 Business Days

Presentation Attributes

Storefront Attributes

Search Refinements

Shop Runner

Battery Features

Capacity UOM

mAh

Rechargeable

No

Cleansing

Dimensions

Fulfillment

Package Height

0.50

Package Length

6.25

Package Width

3.70

General

Model

NTE74HC259

Product Type

Inverters and decoders

Identification

Manufacturer Part Number

NTE74HC259

Surcharge

Legal

Merchandising

Inputs & Outputs

Miscellaneous Features

Operating Temperature UOM

° F

Supported Languages

English

Power Features

Docking station

No

Promo

Retail

Price

Remote Control Features

Warranty

0.00

0.00

Available RadioShack Service Plan

No

Warranty Labor UOM

days

Warranty Parts UOM

days

Root

Additional Features

Water-Resistant or Waterproofness Standard

No

Miscellaneous Features

Power Features

Print
 

Summary

The NTE74HC259 is an 8−bit addressable latch in a 16−lead DIP-type package that features the low−power consumption associated with CMOS circuitry and has speeds comparable to low−power Schottky. This latches three active modes and one reset mode. When both the Latch Enable (LE) and Master Reset (MR) inputs are low (8−line demultiplexer mode) the output of the addressed latch follows the data input and all other outputs are forced low. When both MR and LE are high (memory mode), all outputs are isolated from the data input, i.e. all latches hold the last data presented before the LE transition from low to high. A condition of LE low and MR high (addressable latch mode) allows the addressed latch’s output to follow the data input, all other latches are unaffected. The reset mode (all outputs low) results when LE is high and MR is low.
  • Wide-power supply range: 2V to 6V
  • High-noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Buffered inputs and outputs
  • Four operating modes
  • Typical propagation delay: 15ns at VCC = 5V, CL = 15pF, TA = +25°C
  • Fanout (over temp range): standard outputs 10 LS−TTL loads, bus driver outputs 15 LS−TTL loads
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LS−TTL logic ICs

Tech Specs

The NTE74HC259 is an 8−bit addressable latch in a 16−lead DIP-type package that features the low−power consumption associated with CMOS circuitry and has speeds comparable to low−power Schottky. This latches three active modes and one reset mode. When both the Latch Enable (LE) and Master Reset (MR) inputs are low (8−line demultiplexer mode) the output of the addressed latch follows the data input and all other outputs are forced low. When both MR and LE are high (memory mode), all outputs are isolated from the data input, i.e. all latches hold the last data presented before the LE transition from low to high. A condition of LE low and MR high (addressable latch mode) allows the addressed latch’s output to follow the data input, all other latches are unaffected. The reset mode (all outputs low) results when LE is high and MR is low.

Reviews

$ $1.70 In Stock