• Model: NTE74H72
  • Catalog #: 55050966

NTE74H72- IC TTL JK M/S Flip-Flop

Details

$4.00

In Stock

(Online Only)

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE74H72 is a high-speed J−K master/slave flip−flop with AND gated inputs in a 14−Lead DIP-type package. The AND gate inputs for entry into the master section are controlled by the clock pulse. The clock pulse also regulates the circuitry which connects the master and slave sections.
The sequence of operation is as follows:
1) Isolate slave from master
2) Enter information from AND gate inputs to master
3) Disable AND gate inputs
4) Transfer information from master to slave

Logic state of J and K inputs must not be allowed to change when the clock pulse is in HIGH state.
  • Recommended operating conditions:
    VCC: 4.5-+5.5VDC
  • TA: 0-70°C, 25°C Typ
  • Fan out from each output: 12.5U.L.
  • tp(clock): 12ns min
  • tp(preset): 16ns min
  • tsetup: ≥tp(clock)
  • thold: 2
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Shipping

Ships in 1-2 Business Days

Presentation Attributes

Storefront Attributes

Search Refinements

Shop Runner

Battery Features

Capacity UOM

mAh

Rechargeable

No

Cleansing

Dimensions

Fulfillment

Package Height

0.50

Package Length

6.25

Package Width

3.70

General

Model

NTE74H72

Product Type

Flip-flops

Identification

Manufacturer Part Number

NTE74H72

Surcharge

Legal

Merchandising

Inputs & Outputs

Miscellaneous Features

Operating Temperature UOM

° F

Supported Languages

English

Power Features

Docking station

No

Promo

Retail

Price

Remote Control Features

Warranty

0.00

0.00

Available RadioShack Service Plan

No

Warranty Labor UOM

days

Warranty Parts UOM

days

Root

Additional Features

Water-Resistant or Waterproofness Standard

No

Miscellaneous Features

Power Features

Print
 

Summary

The NTE74H72 is a high-speed J−K master/slave flip−flop with AND gated inputs in a 14−Lead DIP-type package. The AND gate inputs for entry into the master section are controlled by the clock pulse. The clock pulse also regulates the circuitry which connects the master and slave sections.
The sequence of operation is as follows:
1) Isolate slave from master
2) Enter information from AND gate inputs to master
3) Disable AND gate inputs
4) Transfer information from master to slave

Logic state of J and K inputs must not be allowed to change when the clock pulse is in HIGH state.
  • Recommended operating conditions:
    VCC: 4.5-+5.5VDC
  • TA: 0-70°C, 25°C Typ
  • Fan out from each output: 12.5U.L.
  • tp(clock): 12ns min
  • tp(preset): 16ns min
  • tsetup: ≥tp(clock)
  • thold: 2

Tech Specs

The NTE74H72 is a high-speed J−K master/slave flip−flop with AND gated inputs in a 14−Lead DIP-type package. The AND gate inputs for entry into the master section are controlled by the clock pulse. The clock pulse also regulates the circuitry which connects the master and slave sections.
The sequence of operation is as follows:
1) Isolate slave from master
2) Enter information from AND gate inputs to master
3) Disable AND gate inputs
4) Transfer information from master to slave

Logic state of J and K inputs must not be allowed to change when the clock pulse is in HIGH state.

Reviews