• Model: NTE74278
  • Catalog #: 55051352

NTE74278 IC TTL 4-Bit Register

Details

$3.76

In Stock

(Online Only)

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE74278 is a 4-bit cascadable priority register in a 14-lead plastic DIP-type package consisting of four data latches, full priority output gating and a cascading gate. The highest-order data applied at a D latch input is transferred to the appropriate Y output while the strobe input is high and when the strobe goes low all data is latched. The cascading input P0 is fully overriding and on the highest-order package this input must be held at a low logic level. The P1 output is intended for connection to the P0 input of the next lower-order package and will provide a "busy" (high-level) signal to inhibit all subsequent lower-order packages. After the overriding P0 input, the order of priority is D1, D2, D3 and D4 respectively within the package.

Features:
  • Latched data inputs serve as buffer register and can also: Synchronize data acquisition
    Debounce mechanical switch input
  • Cascading input P0 and output P1 provide "Busy" signal, inhibiting all lower-order bits
  • Full TTL compatibility

  • Applications:
  • Priority interrupt
  • Synchronous priority line selection


  • Data Sheet
    • Absolute Maximum Ratings:
      Unless otherwise specified, all voltages are referenced to GND
    • Supply voltage, VCC: 7V
    • DC input voltage, VIN: 5.5V
    • Interemitter voltage (voltage between 2 emitters of a multiple−emitter transistor)*: 5.5V
    • Operating temperature range, TA: 0°C to +70°C
    • Storage temperature range, Tstg: −65°C to +150°C
    *For this circuit, this rating applies between the clear and count/load inputs.
    Pricing and availability: Please note that all prices are subject to change without prior notice. Prices advertised on this site are for online orders only. Prices on some items may differ from those advertised in RadioShack stores. All merchandise may not be available at all stores, and all stores may not participate in all sales promotions. We recommend you contact the store to confirm product availability and price.

    Shipping

    Ships in 1-2 Business Days

    Presentation Attributes

    Storefront Attributes

    Search Refinements

    Shop Runner

    Battery Features

    Capacity UOM

    mAh

    Rechargeable

    No

    Cleansing

    Dimensions

    Fulfillment

    Package Height

    0.50

    Package Length

    6.25

    Package Width

    3.70

    General

    Model

    NTE74278

    Product Type

    Registers and buffers

    Identification

    Manufacturer Part Number

    NTE74278

    Surcharge

    Legal

    Merchandising

    Inputs & Outputs

    Miscellaneous Features

    Operating Temperature UOM

    ° F

    Supported Languages

    English

    Power Features

    Docking station

    No

    Promo

    Retail

    Price

    Remote Control Features

    Warranty

    0.00

    0.00

    Available RadioShack Service Plan

    No

    Warranty Labor UOM

    days

    Warranty Parts UOM

    days

    Root

    Additional Features

    Water-Resistant or Waterproofness Standard

    No

    Miscellaneous Features

    Power Features

    Print
     

    Summary

    The NTE74278 is a 4-bit cascadable priority register in a 14-lead plastic DIP-type package consisting of four data latches, full priority output gating and a cascading gate. The highest-order data applied at a D latch input is transferred to the appropriate Y output while the strobe input is high and when the strobe goes low all data is latched. The cascading input P0 is fully overriding and on the highest-order package this input must be held at a low logic level. The P1 output is intended for connection to the P0 input of the next lower-order package and will provide a "busy" (high-level) signal to inhibit all subsequent lower-order packages. After the overriding P0 input, the order of priority is D1, D2, D3 and D4 respectively within the package.

    Features:
  • Latched data inputs serve as buffer register and can also: Synchronize data acquisition
    Debounce mechanical switch input
  • Cascading input P0 and output P1 provide "Busy" signal, inhibiting all lower-order bits
  • Full TTL compatibility

  • Applications:
  • Priority interrupt
  • Synchronous priority line selection


  • Data Sheet
    • Absolute Maximum Ratings:
      Unless otherwise specified, all voltages are referenced to GND
    • Supply voltage, VCC: 7V
    • DC input voltage, VIN: 5.5V
    • Interemitter voltage (voltage between 2 emitters of a multiple−emitter transistor)*: 5.5V
    • Operating temperature range, TA: 0°C to +70°C
    • Storage temperature range, Tstg: −65°C to +150°C

    Tech Specs

    The NTE74278 is a 4-bit cascadable priority register in a 14-lead plastic DIP-type package consisting of four data latches, full priority output gating and a cascading gate. The highest-order data applied at a D latch input is transferred to the appropriate Y output while the strobe input is high and when the strobe goes low all data is latched. The cascading input P0 is fully overriding and on the highest-order package this input must be held at a low logic level. The P1 output is intended for connection to the P0 input of the next lower-order package and will provide a "busy" (high-level) signal to inhibit all subsequent lower-order packages. After the overriding P0 input, the order of priority is D1, D2, D3 and D4 respectively within the package.

    Features:
  • Latched data inputs serve as buffer register and can also: Synchronize data acquisition
    Debounce mechanical switch input
  • Cascading input P0 and output P1 provide "Busy" signal, inhibiting all lower-order bits
  • Full TTL compatibility

  • Applications:
  • Priority interrupt
  • Synchronous priority line selection


  • Data Sheet

    Reviews

    $ $3.76 In Stock