• Model: NTE74HCT161
  • Catalog #: 55051022

NTE NTE74HCT161 IC High-Speed CMOS Counter

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$1.43

In Stock

(Online Only)

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE74HCT161 (Asynchronous Clear) and NTE74HCT163 (Synchronous Clear) are synchronous presettable counters in a 16−Lead DIP-type package that utilize microCMOS Technology, 3.0 micron silicon-gate N−well CMOS, and internal look−ahead carry logic for use in high-speed counting applications. They offer the high-noise immunity and low-power consumption inherent to CMOS with speeds similar to low-power Schottky TTL. All flip−flops are clocked simultaneously on the low-to-high-to-transition (positive−edge) of the CLOCK input waveform. These counters may be preset using the LOAD input. Presetting of all four flip−flops is synchronous to the rising edge of CLOCK. When LOAD is held low, counting is disabled and the data on the A, B, C and D inputs is loaded into the counter on the rising edge of CLOCK. If the load input is taken high before the positive edge of CLOCK, the count operation will be unaffected. Both of these counters may be cleared by utilizing the CLEAR input. The clear function on the NTE74HCT163 counter is synchronous to the clock. That is, the counter is cleared on the positive edge of CLOCK while the clear input is held low. The NTE74HCT161 counter is cleared asynchronously. When the CLEAR is taken low, the counter is cleared immediately, regardless of the CLOCK. Two active high enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are provided to enable easy cascading of counters. Both ENABLE inputs must be high to count. The ENT input also enables the RC output. When enabled, the RC outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the high-level portion of the QA output. The RC output is fed to successive cascaded stages to facilitate easy implementation of N−bit counters. These circuits are TTL input and output compatible and all inputs are protected from damage due to static discharge by diodes to VCC and GND.
  • Typical operating frequency: 40MHz
  • Typical propagation delay: clock to Q: 18ns
  • Low quiescent current: 80μA (max)
  • Low-input current: 1μA (max)
  • Wide-power supply range: 2V to 6V
  • TTL input compatible inputs
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Shipping

Ships in 1-2 Business Days

Presentation Attributes

Storefront Attributes

Search Refinements

Shop Runner

Battery Features

Capacity UOM

mAh

Rechargeable

No

Cleansing

Dimensions

Fulfillment

Package Height

0.50

Package Length

6.25

Package Width

3.70

General

Model

NTE74HCT161

Product Type

Counters

Identification

Manufacturer Part Number

NTE74HCT161

Surcharge

Legal

Merchandising

Inputs & Outputs

Miscellaneous Features

Operating Temperature UOM

° F

Supported Languages

English

Power Features

Docking station

No

Promo

Retail

Price

Remote Control Features

Warranty

0.00

0.00

Available RadioShack Service Plan

No

Warranty Labor UOM

days

Warranty Parts UOM

days

Root

Additional Features

Water-Resistant or Waterproofness Standard

No

Miscellaneous Features

Power Features

Print
 

Summary

The NTE74HCT161 (Asynchronous Clear) and NTE74HCT163 (Synchronous Clear) are synchronous presettable counters in a 16−Lead DIP-type package that utilize microCMOS Technology, 3.0 micron silicon-gate N−well CMOS, and internal look−ahead carry logic for use in high-speed counting applications. They offer the high-noise immunity and low-power consumption inherent to CMOS with speeds similar to low-power Schottky TTL. All flip−flops are clocked simultaneously on the low-to-high-to-transition (positive−edge) of the CLOCK input waveform. These counters may be preset using the LOAD input. Presetting of all four flip−flops is synchronous to the rising edge of CLOCK. When LOAD is held low, counting is disabled and the data on the A, B, C and D inputs is loaded into the counter on the rising edge of CLOCK. If the load input is taken high before the positive edge of CLOCK, the count operation will be unaffected. Both of these counters may be cleared by utilizing the CLEAR input. The clear function on the NTE74HCT163 counter is synchronous to the clock. That is, the counter is cleared on the positive edge of CLOCK while the clear input is held low. The NTE74HCT161 counter is cleared asynchronously. When the CLEAR is taken low, the counter is cleared immediately, regardless of the CLOCK. Two active high enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are provided to enable easy cascading of counters. Both ENABLE inputs must be high to count. The ENT input also enables the RC output. When enabled, the RC outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the high-level portion of the QA output. The RC output is fed to successive cascaded stages to facilitate easy implementation of N−bit counters. These circuits are TTL input and output compatible and all inputs are protected from damage due to static discharge by diodes to VCC and GND.
  • Typical operating frequency: 40MHz
  • Typical propagation delay: clock to Q: 18ns
  • Low quiescent current: 80μA (max)
  • Low-input current: 1μA (max)
  • Wide-power supply range: 2V to 6V
  • TTL input compatible inputs

Tech Specs

The NTE74HCT161 (Asynchronous Clear) and NTE74HCT163 (Synchronous Clear) are synchronous presettable counters in a 16−Lead DIP-type package that utilize microCMOS Technology, 3.0 micron silicon-gate N−well CMOS, and internal look−ahead carry logic for use in high-speed counting applications. They offer the high-noise immunity and low-power consumption inherent to CMOS with speeds similar to low-power Schottky TTL. All flip−flops are clocked simultaneously on the low-to-high-to-transition (positive−edge) of the CLOCK input waveform. These counters may be preset using the LOAD input. Presetting of all four flip−flops is synchronous to the rising edge of CLOCK. When LOAD is held low, counting is disabled and the data on the A, B, C and D inputs is loaded into the counter on the rising edge of CLOCK. If the load input is taken high before the positive edge of CLOCK, the count operation will be unaffected. Both of these counters may be cleared by utilizing the CLEAR input. The clear function on the NTE74HCT163 counter is synchronous to the clock. That is, the counter is cleared on the positive edge of CLOCK while the clear input is held low. The NTE74HCT161 counter is cleared asynchronously. When the CLEAR is taken low, the counter is cleared immediately, regardless of the CLOCK. Two active high enable inputs (ENP and ENT) and a RIPPLE CARRY (RC) output are provided to enable easy cascading of counters. Both ENABLE inputs must be high to count. The ENT input also enables the RC output. When enabled, the RC outputs a positive pulse when the counter overflows. This pulse is approximately equal in duration to the high-level portion of the QA output. The RC output is fed to successive cascaded stages to facilitate easy implementation of N−bit counters. These circuits are TTL input and output compatible and all inputs are protected from damage due to static discharge by diodes to VCC and GND.

Reviews

$ $1.43 In Stock