• Model: NTE40160B
  • Catalog #: 55050781

NTE NTE40160B IC-CMOS Synchronous Programmable 4−Bit Counter

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$4.60

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(Online Only)

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Additional Information

  • Summary
  • Tech Specs
  • Reviews
The NTE40160B (decade w/ asynchronous clear), NTE40161B (binary w/ asynchronous clear), NTE40162B (decade w/ synchronous clear) and NTE40163B (binary w/ synchronous clear) are 4−bit synchronous programmable counters in a 16−lead DIP type package. The CLEAR function of the NTE40162B and NTE40163B is synchronous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the NTE40160B and NTE40161B is asynchronous and a low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK, LOAD or ENABLE inputs. A low level at the LOAD input disables the counter and causes the output to agree with the setup data after the next CLOCK pulse regardless of the conditions of the ENABLE inputs. The carry look−ahead circuitry provides for cascading counters for n−bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count−enable inputs and a carry output (COUT). Counting is enabled when both PE and TE inputs are high. The TE input is fed forward to enable COUT. This enabled output produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic transitions at the PE or TE inputs may occur when the clock is either high or low.
  • Internal look−ahead for fast counting
  • Carry output for cascading
  • Synchronous programmable
  • Clear asynchronous input: NTE40160B, NTE40161B
  • Clear synchronous input: NTE40162B, NTE40163B
  • Synchronous load control input
  • Low−power TTL compatibility
  • Standardized, symmetrical output characteristics
  • Maximum input current of 1μA at 18V over full package temperature range: 100nA at 18V and +25°C
  • Noise margin (over full package temperature range):
  • 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
  • 5V, 10V and 15V parametric ratings
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Ships in 1-2 Business Days

Presentation Attributes

Storefront Attributes

Search Refinements

Shop Runner

Power Reviews

Battery Features

Capacity UOM

mAh

Rechargeable

No

Cleansing

Dimensions

Fulfillment

Package Height

0.50

Package Length

6.25

Package Width

3.70

General

Model

NTE40160B

Product Type

Counters

Identification

Manufacturer Part Number

NTE40160B

Surcharge

Legal

Merchandising

Inputs & Outputs

Miscellaneous Features

Operating Temperature UOM

° F

Supported Languages

English

Power Features

Docking station

No

Promo

Retail

Price

Remote Control Features

Warranty

0.00

0.00

Available RadioShack Service Plan

No

Warranty Labor UOM

days

Warranty Parts UOM

days

Root

Additional Features

Water-Resistant or Waterproofness Standard

No

Miscellaneous Features

Power Features

Print
 

Summary

The NTE40160B (decade w/ asynchronous clear), NTE40161B (binary w/ asynchronous clear), NTE40162B (decade w/ synchronous clear) and NTE40163B (binary w/ synchronous clear) are 4−bit synchronous programmable counters in a 16−lead DIP type package. The CLEAR function of the NTE40162B and NTE40163B is synchronous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the NTE40160B and NTE40161B is asynchronous and a low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK, LOAD or ENABLE inputs. A low level at the LOAD input disables the counter and causes the output to agree with the setup data after the next CLOCK pulse regardless of the conditions of the ENABLE inputs. The carry look−ahead circuitry provides for cascading counters for n−bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count−enable inputs and a carry output (COUT). Counting is enabled when both PE and TE inputs are high. The TE input is fed forward to enable COUT. This enabled output produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic transitions at the PE or TE inputs may occur when the clock is either high or low.
  • Internal look−ahead for fast counting
  • Carry output for cascading
  • Synchronous programmable
  • Clear asynchronous input: NTE40160B, NTE40161B
  • Clear synchronous input: NTE40162B, NTE40163B
  • Synchronous load control input
  • Low−power TTL compatibility
  • Standardized, symmetrical output characteristics
  • Maximum input current of 1μA at 18V over full package temperature range: 100nA at 18V and +25°C
  • Noise margin (over full package temperature range):
  • 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
  • 5V, 10V and 15V parametric ratings

Tech Specs

The NTE40160B (decade w/ asynchronous clear), NTE40161B (binary w/ asynchronous clear), NTE40162B (decade w/ synchronous clear) and NTE40163B (binary w/ synchronous clear) are 4−bit synchronous programmable counters in a 16−lead DIP type package. The CLEAR function of the NTE40162B and NTE40163B is synchronous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the NTE40160B and NTE40161B is asynchronous and a low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK, LOAD or ENABLE inputs. A low level at the LOAD input disables the counter and causes the output to agree with the setup data after the next CLOCK pulse regardless of the conditions of the ENABLE inputs. The carry look−ahead circuitry provides for cascading counters for n−bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count−enable inputs and a carry output (COUT). Counting is enabled when both PE and TE inputs are high. The TE input is fed forward to enable COUT. This enabled output produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic transitions at the PE or TE inputs may occur when the clock is either high or low.

Reviews